1. Field of the Invention
The present invention relates to a multiprocessor system including asymmetric processors having dissimilar control and data-handling characteristics. More specifically, the present invention relates to a system and method for handling interrupts and exceptions in an asymmetric multiprocessor system.
2. Description of the Related Art
General-purpose processors typically include circuits and structures for handling interrupts and exceptions. An interrupt is an event that causes a processor to stop execution of a current instruction thread and begin execution of an interrupt service instruction thread that is designated and activated by an interrupt handler. When the interrupt service instruction thread has completed execution, the current instruction thread continues executing. Interrupts are external events in the sense that the cause of an interrupt is not directly related to the execution of instructions in the current instruction thread. Interrupts are typically handled by saving the state or context of the processor, executing a servicing routine, and then restoring the state or context of the processor and resuming the interrupted execution thread.
An exception is a event that is caused by either the execution of an instruction or an attempt to execute an instruction by a processor, the execution of which is inconsistent with the current state of the processor. Examples of events that cause an exception condition include an attempt to execute an illegal or undefined instruction by a processor, an attempt to execute an instruction when the instruction address or data address are unaligned, a protection error, a set breakpoint, a division by zero, and an overflow condition during execution of an arithmetic instruction. A processor responds to an exception condition by executing an exception handler instruction thread. Exceptions are conventionally handled by executing a selected set of instructions depending on the particular type of condition that caused the exception condition.
The interrupt and exception handling mechanisms that are used in multiprocessor architecture systems are generally inefficient for usage in an asymmetric multiprocessor system with processors having dissimilar control and data-handling characteristics since the control operations inherent to interrupt and exception handling are quickly and easily performed by general-purpose processors and substantially more difficult for large context vector processors. Operations of multiprocessor systems that are handled using exceptions and interrupts often involve saving of the state of the processors including saving of registers and data that are currently undergoing processing. A processor with many large registers does not easily save and reload the processor state during operations such as multiple processor context switching.
What is needed is a multiprocessor architecture that facilitates exception and interrupt handling for asymmetric processors including a large machine state or context.